During the fabrication of semiconductor devices, such as flash memory devices, it is necessary, following the formation of stack gates, control lines, etc., to fill the gaps therebetween. However, with the ever diminishing size and spacing with which these elements are formed, effective filing of the gaps between the stack gates and/or associated electrically conducive lines/elements which interconnect the gates, with conventional plasma based chemical vapor deposition (CVD) oxide, has become ever difficult to achieve.
In particular, the gap which is defined between two stacked gates 101, 102 of the nature shown in FIG. 1, when filled with boron-phosphorus doped silicate glass, (BPSG) silicone oxide derived from tetraethylorthosilicate (TEOS) or phosphorus doped silicate glass (PSG) deposition is, as shown in FIG. 2, apt to result in a void of the nature denoted by V. This void can be removed only after a relatively long thermal cycle of 850.degree. C. for about 3 minutes, wherein the insulation film 104 is melted and permitted to soften, settle and close the void. However, as the design rules shrink to about 0.18.mu. and under, with a gap distances of about 0.2.mu. to about 0.3.mu., this thermal cycle can no longer be tolerated and therefore it is necessary to be avoid the formation of voids without the use of such high temperature techniques.
Another problem encountered with the formation of the above type of memory, is that CMP (chemical-mechanical polishing) is employed to dress the upper surface of the dielectric layer which is used to encase the gate stacks. In this connection, it is usual to provide a sacrificial cap layer and to subject this layer to CMP. However, during this process in particular, mobile ionic contamination tends to be generated, and leads to the drawback that contaminating particles/ions find their way into the underlying layers and deteriorate the performance of the various elements.
Accordingly, there exists a need for methodology enabling the formation of flash memory devices having a design rule of about 0.18.mu. or less, without the need of the above mentioned thermal cycle and such that mobile ionic contamination during the formation of such structures are entrapped.